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X25401 1 spi serial autostore? novram ? xicor, inc. 1992, 1995, 1996 patents pending characteristics subject to change without notice 2051-1.5 8/1/97 t0/c0/d2 sh description the xicor X25401 is a serial 256 bit novram featuring a static ram configured 16 x 16, overlaid bit-by-bit with a nonvolatile e 2 prom array. the X25401 features a serial peripheral interface (spi) and software protocol allowing operation on a simple three-wire bus. the bus signals are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is con- trolled through a chip select ( cs ) input, allowing any number of devices to share the same bus. the xicor novram design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. a store opera- tion (ram data to e 2 prom) is completed in 5ms or less and a recall operation (e 2 prom data to ram) is com- pleted in 2 m s or less. the X25401 also includes the autostore feature, a user selectable feature that automatically performs a store operation when v cc falls below a preset threshold. xicor novrams are designed for unlimited write opera- tions to ram, either from the host or recalls from e 2 prom and a minimum 1,000,000 store operations. inherent data retention is specified to be greater than 100 years. features ? 1mhz clock rate ? autostore? novram automatically performs a store operation upon loss of v cc ? single 5 volt supply ? ideal for use with single chip microcomputers minimum i/o interface spi mode (0,0 & 1,1) serial port compatible easily interfaced to microcontroller ports ? software and hardware control of nonvolatile functions ? auto recall on power-up ? ttl and cmos compatible ? low power dissipation active current: 10ma standby current: 50 m a ? 8-lead pdip and 8-lead soic packages ? high reliability store cycles: 1,000,000 data retention: 100 years 256 bit X25401 16 x 16 bit autostore? novram is a trademark of xicor, inc. cops is a trademark of national semiconductor corp. functional diagram nonvolatile e 2 prom control logic column decode row decode 4-bit counter instruction decode instruction register cs (1) si (3) sck (2) so (4) recall (6) as (7) static ram 256-bit recall store 2051 fhd f01 a pplication n ote available an56
2 X25401 pin configuration pin descriptions chip select ( cs ) the chip select input must be low to enable all read/ write operations. cs must remain low following a read or write command until the data transfer is com- plete. cs high places the X25401 in the low power standby mode and resets the instruction register. there- fore, cs must be brought high after the completion of an operation in order to reset the instruction register in preparation for the next command. serial clock (sck) the serial clock input is used to clock all data into and out of the device. serial data in (si) si is the serial data input. serial data out (so) so is the serial data output. it is in the high impedance state except during data output cycles in response to a read instruction. autostore output ( as ) as is an open drain output which, when asserted indi- cates v cc has fallen below the autostore thresh- old (v asth ). as may be wire-ored with multiple open drain outputs and used as an interrupt input to a micro- controller or as an input to a low power reset circuit. recall recall low will initiate an internal transfer of data from e 2 prom to the ram array. pin names symbol description cs chip enable sck serial clock si serial data in so serial data out recall recall input as autostore output v cc +5v v ss ground 2051 pgm t01 cs sck si so 1 2 3 4 8 7 6 5 v cc as recall v ss X25401 2051 fhd f02 dip/soic
X25401 3 device operation the X25401 contains an 8-bit instruction register. it is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire data transfer operation. table 1 contains a list of the instructions and their operation codes. the most significant bit (msb) of all instructions is a logic one (high), bits 6 through 3 are either ram address bits (a) or dont cares (x) and bits 2 through 0 are the operation codes. the X25401 requires the instruction to be shifted in with the msb first. after cs is low, the X25401 will not begin to interpret the data stream until a logic 1 has been shifted in on si. therefore, cs may be brought low with sck running and si low. si must then go high to indicate the start condition of an instruction before the X25401 will begin any action. in addition, the sck clock is totally static. the user can completely stop the clock and data shifting will be stopped. restarting the clock will resume shifting of data. rcl and recall either a software rcl instruction or a low on the recall input will initiate a transfer of e 2 prom data into ram. this software or hardware recall operation sets an internal previous recall latch. this latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. al- though a recall operation is performed upon power-up, the previous recall latch is not set by this operation. wrds and wren internally the X25401 contains a write enable latch. this latch must be set for either writes to the ram or store operations to the e 2 prom. the wren instruction sets the latch and the wrds instruction resets the latch, disabling both ram writes and e 2 prom stores, effec- tively protecting the nonvolatile data from corruption. the write enable latch is automatically reset on power-up. sto the software sto instruction will initiate a transfer of data from ram to e 2 prom. in order to safeguard against unwanted store operations, the following con- ditions must be true: ? sto instruction issued. ? the internal write enable latch must be set (wren instruction issued). ? the previous recall latch must be set (either a software or hardware recall operation). once the store cycle is initiated, all other device func- tions are inhibited. upon completion of the store cycle, the write enable latch is reset. refer to figure 4 for a state diagram description of enabling/disabling condi- tions for store operations. table 1. instruction set instruction format, i 2 i 1 i 0 operation wrds (figure 3) 1xxxx000 reset write enable latch (disables writes and stores) sto (figure 3) 1xxxx001 store ram data in e 2 prom enas 1xxxx010 enable autostore feature write (figure 2) 1aaaa011 write data into ram address aaaa wren (figure 3) 1xxxx100 set write enable latch (enables writes and stores) rcl (figure 3) 1xxxx101 recall e 2 prom data into ram read (figure 1) 1aaaa11x read data from ram address aaaa 2051 pgm t11 x = dont care a = address
4 X25401 write the write instruction contains the 4-bit address of the word to be written. the write instruction is immedi- ately followed by the 16-bit word to be written. cs must remain low during the entire operation. cs must go high before the next rising edge of sck. if cs is brought high prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to ram. if cs is kept low for more than 24 sck clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. read the read instruction contains the 4-bit address of the word to be accessed. unlike the other six instructions, i 0 of the instruction word is a dont care. this provides two advantages. in a design that ties both si and so together, the absence of an eighth bit in the instruction allows the host time to convert an i/o line from an output to an input. secondly, it allows for valid data output during the ninth sck clock cycle. all data bits are clocked by the falling edge of sck (refer to read cycle diagram). low power mode when cs is high, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. autostore feature the autostore instruction (enas) sets the autostore enable latch, allowing the X25401 to automatically perform a store operation when v cc falls below the autostore threshold (v asth ). write protection the X25401 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. power-up condition upon power-up the write enable and autostore enable latches are in the reset state, disabling any store operation. unknown data store the previous recall latch must be set after power-up. it may be set only by performing a software or hard- ware recall operation, which assures that data in all ram locations is valid. system considerations power-up recall the X25401 performs a power-up recall that transfers the e 2 prom contents to the ram array. although the data may be read from the ram array, this recall does not set the previous recall latch. during this power-up recall operation, all commands are ignored. therefore, the host should delay any operations with the X25401 a minimum of t pur after v cc is stable.
X25401 5 figure 1. ram read figure 2. ram write figure 3. non-data operations 2051 fhd f09.1 1 cs 2345678 1a 1 aaa 1x* sck si 9 101112222324 d 1 d 2 d 3 d 14 d 15 d 0 d 13 so high z *bit 8 of read instructions is dont care d 0 2051 fhd f10.1 1 cs 2345678 1a 1 aaa 1 sk di 9 101121222324 d 0 d 1 d 2 d 12 d 13 d 14 d 15 0 2051 fhd f11.1 1 cs 2345678 1x i 2 xxx i 1 i 0 sck si
6 X25401 figure 4. X25401 state diagram power on store enabled ram read or write ram read enabled ram read enabled ram read & write enabled wren command ram read ram read power-up recall rcl command or recall sto or wrds cmd ram read & write enabled store enabled autostore enabled ram read or write enas command wren command sto or wrds cmd power off autostore power down 2051 fhd f12.1
X25401 7 absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 2051 pgm t02.1 supply voltage limits X25401 5v 10% 2051 pgm t03.2 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. endurance and data retention parameter min. units endurance 100,000 data changes per bit store cycles 1,000,000 store cycles data retention 100 years 2051 pgm t05 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc supply current 10 ma sck = 0.4v/2.4v levels @ 1mhz, (ttl inputs) so = open, all other inputs = v ih i cc2 v cc supply current 2 ma all inputs = v ih , cs = v il (during autostore) so = open, v cc = 4.3v i sb1 v cc standby current 1 ma so = open, cs = v il , (ttl inputs) all other inputs = v ih i sb2 v cc standby current 50 m a so = open, cs = v ss (cmos inputs) all other inputs = v cc C 0.3v i li input load current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc v ll (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 4.2ma v oh output high voltage 2.4 v i oh = C2ma v ol(as) output low voltage (as) 0.4 v i ol (as) = 1ma 2051 pgm t04.3 capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c out (2) output capacitance 8 pf v out = 0v c in (2) input capacitance 6 pf v in = 0v 2051 pgm t06.2
8 X25401 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 2051 pgm t07.1 equivalent a.c. load circuit a.c. characteristics (over the recommended operating conditions unless otherwise specified.) power-up timing symbol parameter max. units t pur (4) power-up to read operation 200 m s t puw (4) power-up to write or store operation 5 ms 2051 pgm t09 notes: (3) sck rise and fall times must be less than 50ns. (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. read and write cycle limits symbol parameter min. max. units f sk (3) sck frequency 1 mhz t sckh sck positive pulse width 400 ns t sckl sck negative pulse width 400 ns t ds data setup time 400 ns t dh data hold time 80 ns t pd1 sck to data bit 0 valid 375 ns t pd sck to data valid 375 ns t z chip select to output high z 1 m s t css chip select setup 800 ns t csh chip select hold 350 ns t cds chip deselect 800 ns 2051 pgm t08.1 2051 fhd f03 5v 919 w 497 w output 100pf
X25401 9 write cycle read cycle 2051 fhd f04.1 sck x12n cs si sck cycle # t css t sckh 1/f sck t sckl t csh t cds t dh t ds 2051 fhd f05.1 sck 678910n d0 d1 dn high z high z cs si so dont care sk cycle # 12 i1 t pd1 t pd t z
10 X25401 nonvolatile operations previous software write enable recall latch operation recall instruction latch state state hardware recall 0 nop (5) xx software recall 1 rcl x x software store 1 sto set set 2051 pgm t10 array recall limits symbol parameter min. max. units t rcc recall cycle time 2 m s t rcp recall pulse width (6) 500 ns t rcz recall to output in high z 500 ns 2051 pgm t11 recall timing software store cycle limits symbol parameter min. typ. (7) max. units t st store time after clock 8 of sto command 2 5 ms 2051 pgm t12.1 notes: (5) nop designates when the X25401 is not currently executing an instruction. (6) recall rise time must be <10 m s. (7) typical values are for t a = 25 c and nominal supply voltage. 2051 fhd f06 t rcc t rcp t rcz high z recall so
X25401 11 autostore cycle limits symbol parameter min. max. units v asto autostore cycle time 5 ms v asth autostore threshold voltage 4.0 4.3 v v asend autostore cycle end voltage 3.5 v 2051 pgm t13 autostore cycle timing diagrams symbol table 2051 fhd f08 as t pur t asto t pur 0v v asth v cc 1 2 3 4 5 v cc volts (v) time (ms) v asth v asend autostore cycle in progress t asto store time waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
12 X25401 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X25401 13 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
14 X25401 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. ordering information device X25401 p t -v v cc limits blank = 5v 10% temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c package p = 8-lead plastic dip s = 8-lead soic

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